Dual-mode operation of application specific integrated circuits

An integrated circuit comprising:

• multiple delay registers each connected to a corresponding first bus line;
• multiple tiles, each tile of a first group of the tiles connected to a corresponding second bus line, and each tile of a second group of the tiles connected to a corresponding one of the first bus lines;
• and
• a controller configured to:
• determine a configuration of the first and second groups of tiles for execution of a computation;
• when the configuration for the tiles satisfies a first criterion, control the integrated circuit to operate in a first mode in which respective input data for the computation is concurrently received at each of the multiple tiles via the first and second bus lines;
• and
• when the configuration for the tiles satisfies a second criterion, control the integrated circuit to operate in a second mode, in which:
• at a first time, respective first input data for the computation is concurrently received at each tile of the first group of tiles;
• at the first time, second input data for the computation is stored in each of the delay registers;
• and
• at a second time, the second input data is released from the delay registers and the respective second input data is received at each tile of the second group of tiles.