Trap circuits for use with capacitively-coupled resonant clock networks

A superconducting integrated circuit comprising:

• a clock line coupled:
• (1) to a first Josephson junction via a first capacitor, wherein the first capacitor is configured to receive a clock signal via the clock line and couple a first bias current to the first Josephson junction, and (2) to a second Josephson junction via a second capacitor, wherein the second capacitor is configured to receive a clock signal via the clock line and couple a second bias current to the second Josephson junction;
• and
• a trap circuit coupled between the first capacitor and the first Josephson junction, wherein the trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and any other Josephson junctions capacitively-coupled to the clock line, including the second Josephson junction.

A superconducting integrated circuit comprising:

• a first capacitor for coupling a first Josephson junction to a first node of a first clock line associated with the resonant clock network, wherein the first clock line is configured to provide a first clock signal having a first phase;
• a second capacitor for coupling a second Josephson junction to a second node of the first clock line;
• a third capacitor for coupling a third Josephson junction to a first node of a second clock line associated with the resonant clock network, wherein the second clock line is configured to provide a second clock signal having a second phase different from the first phase;
• a fourth capacitor for coupling a fourth Josephson junction to a second node of the second clock line;
• a first trap circuit coupled between the first capacitor and the first Josephson junction, wherein the first trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and any other Josephson junctions capacitively-coupled to the first clock line, including the second Josephson junction;
• and
• a second trap circuit coupled between the third capacitor and the third Josephson junction, wherein the second trap circuit is configured to attenuate any signals generated by a triggering of the third Josephson junction to reduce crosstalk between the third Josephson junction and any other Josephson junctions capacitively-coupled to the second clock line, including the fourth Josephson junction.