Nmos-based negative charge pump circuit
AssigneeSTMicroelectronics International N.V.
InventorVikas RANA
Life of this patent
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Abstract
A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.
Claims38
A circuit, comprising:
- a first transistor having a source-drain path coupled between an input node and a first node, said input node configured to receive a first voltage;
- a second transistor having a source-drain path coupled between the first node and an output node, said output node configured to generate a second voltage that is more negative than the first voltage;
- a third transistor having a source-drain path coupled between the first node and a first control terminal of the first transistor;
- a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal;
- wherein a logical inversion of the first clock signal is applied to a second control terminal of the second transistor;
- a first bootstrap capacitor having a first plate coupled to the first control terminal and a second plate coupled to receive a second clock signal;
- and
- wherein the first and second clock signals have a same frequency but different duty cycles.
A circuit, comprising:
- a first input transistor having a source-drain path coupled between an input node and a first node, said input node configured to receive a first voltage;
- a second input transistor having a source-drain path coupled between the input node and a second node;
- a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal;
- a first bootstrapping circuit coupled between the first node and a first control terminal of the first input transistor, said first bootstrapping capacitor controlled by a logical inversion of the first clock signal and a second clock signal, wherein the first and second clock signals have a same frequency but different duty cycles;
- a second boost capacitor having a first plate coupled to the second node and a second plate coupled to receive a third clock signal;
- and
- a second bootstrapping circuit coupled between the second node and a second control terminal of the second input transistor, said second bootstrapping capacitor controlled by a logical inversion of the third clock signal and a fourth clock signal, wherein the third and fourth clock signals have a same frequency but different duty cycles.
A circuit, comprising:
- a boost capacitor driven by a first clock signal and coupled to a boost node;
- a bootstrap capacitor driven by a second clock signal and coupled to an intermediate node;
- wherein the first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal;
- an input transistor coupled between an input node and the boost node, wherein a control terminal of the input transistor is coupled to the intermediate node;
- and
- a bootstrap transistor coupled between the boost node and the control terminal of the input transistor, wherein a control terminal of the bootstrap transistor is driven by a logical inverse of the first clock signal.
Dependencies are inferred from the claim text.