Flash memory device with three-dimensional half flash structure and methods for forming the same

An array of flash memory cells comprising:

• a two-dimensional array of flash memory cells, each of the flash memory cells comprising:
• a tunnel dielectric layer on a semiconductor substrate having a first conductivity type;
• a pair of active regions formed in the semiconductor substrate on opposing sides of the tunnel dielectric layer in a first direction, and having a second conductivity type;
• a floating gate electrode on the tunnel dielectric layer;
• a control gate dielectric layer on the floating gate electrode;
• a smaller length control gate electrode on the control gate dielectric layer, wherein a length of the smaller length control gate electrode in the first direction is less than a length of the floating gate electrode in the first direction;
• and
• an electrical contact contacting the control gate dielectric layer and including an outermost sidewall located opposite the control gate electrode and over the floating gate electrode.

A memory cell, comprising:

• a floating gate electrode;
• a control gate dielectric layer on the floating gate electrode and having a first length;
• a control gate on the control gate dielectric layer and having a second length less than the first length;
• and
• a first contact contacting the control gate dielectric layer and including an outermost sidewall located opposite the control gate and over the floating gate electrode.