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US 2022/0285497 A1Published application
Transistor, ternary inverter comprising same, and transistor manufacturing method
AssigneeUnist (Ulsan National Institute of Science and Technology)
InventorsKyung Rok Kim, Ji Won Chang, Jae Won Jeong, Youngeun Choi, Wooseok Kim
Life of this patent
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Abstract
Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.
Claims20
A transistor comprising:
- a constant current formation layer;
- a channel layer provided on the constant current formation layer;
- a pair of source/drain regions spaced apart from each other, with the channel layer therebetween;
- a gate electrode provided on the channel layer;
- and
- a gate ferroelectric film provided between the gate electrode and the channel layer.
3 more elements
A ternary inverter comprising:
- a first well region and a second well region;
- a first constant current formation layer and a second constant current formation layer provided on the first well region and the second well region, respectively;
- a first channel layer and a second channel layer provided on the first constant current formation layer and the second constant current formation layer, respectively;
- a first gate structure and a second gate structure provided on the first channel layer and the second channel layer, respectively;
- a first pair of source/drain regions spaced apart from each other, with the first channel layer therebetween on the first constant current formation layer;
- and
- a second pair of source/drain regions spaced apart from each other, with the second channel layer therebetween on the second constant current formation layer,
- wherein each of the first gate structure and the second gate structure includes a gate ferroelectric film and a gate electrode stacked in this stated order.
5 more elements
A method of manufacturing a transistor, the method comprising:
- providing a constant current formation layer;
- forming a channel layer on the constant current formation layer;
- forming a gate ferroelectric film on the channel layer;
- forming a gate electrode on the channel layer;
- and
- forming a source region and a drain region in the channel layer,
- wherein the source region and the drain region are spaced apart from each other, with the gate electrode therebetween.
4 more elements
Dependencies are inferred from the claim text.