Selective liner on backside via and method thereof

A semiconductor structure, comprising:

• two source/drain (S/D) features;
• one or more channel semiconductor layers connecting the two S/D features;
• a gate structure engaging the one or more channel semiconductor layers, wherein the two S/D features, the one or more channel semiconductor layer, and the gate structure are at a frontside of the semiconductor structure;
• a metal track at a backside of the semiconductor structure;
• a first dielectric layer between the metal track and the one or more channel semiconductor layers;
• a dielectric liner layer on surfaces of the first dielectric layer and spaced away from a first one of the two S/D features by a first gap;
• and
• a via structure connecting the metal track to the first one of the two S/D features, wherein a portion of the via structure is disposed in the first gap.

A semiconductor structure, comprising:

• a source/drain (S/D) feature;
• one or more channel semiconductor layers connected to the S/D feature;
• a gate structure engaging the one or more channel semiconductor layers;
• an interconnect structure over the gate structure and over a frontside of the S/D feature;
• a first dielectric layer below the gate structure;
• a silicide feature on a backside of the S/D feature;
• a dielectric liner layer on surfaces of the first dielectric layer and spaced away from the silicide feature by a first gap;
• and
• a via structure disposed on the silicide feature, wherein a portion of the via structure is disposed in the first gap.