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US 2022/0285491 A1Published application
Transistor source/drain epitaxy blocker
AssigneeQUALCOMM Incorporated
InventorsMing-Huei LIN, Lunwei CHANG, Jun YUAN
Life of this patent
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Abstract
A transistor cell height may be scaled down without producing undesirable degradation with the use of an isolation structure between adjacent fins of a transistor cell. The transistor cell includes a substrate, a first fin and a second fin located on the substrate, and an isolation structure located on the substrate between the first fin and the second fin.
Claims28
An apparatus comprising:
- a substrate;
- a first fin located on the substrate;
- a second fin located on the substrate;
- and
- an isolation structure located on the substrate between the first fin and the second fin.
2 more elements
A method for manufacturing a device, the method comprising:
- providing a substrate;
- forming a first fin located on the substrate;
- forming a second fin located on the substrate;
- and
- forming an isolation structure located on the substrate between the first fin and the second fin.
2 more elements
Dependencies are inferred from the claim text.