Semiconductor device having 3d stacked structure and method of manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• alternately stacking a plurality of insulation layers and a plurality of channel layers on a substrate;
• forming a plurality of cell blocks by etching the plurality of insulation layers and the plurality of channel layers in a direction perpendicular to the substrate;
• forming a plurality of channel recesses by selectively etching the plurality of channel layers between the plurality of insulation layers;
• forming a ferroelectric layer and a gate electrode on each channel layer in each channel recess among the plurality of channel layers and the plurality of channel recesses;
• separating each cell block, among the plurality of cell blocks, by etching the plurality of insulation layers and the plurality of channel layers in the direction perpendicular to the substrate;
• and
• forming a source electrode and a drain electrode on the substrate, the source electrode and the drain electrode extending in the direction perpendicular to the substrate.

A semiconductor device comprising:

• a substrate;
• and
• a cell plate on an upper surface of the substrate,
• the cell plate including a plurality of insulation layers and a plurality of cell layers alternately stacked on the upper surface of the substrate,
• each of the plurality of cell layers including a gate electrode extending in a first direction and a plurality of channel structures, the plurality of channel structures being spaced apart from each other in the first direction and connected to the gate electrode, each of the plurality of channel structures including a channel layer and a ferroelectric layer between the gate electrode and the channel layer,
• the cell plate including a plurality of source electrodes and a plurality of drain electrodes on the upper surface of the substrate and alternately arranged and spaced apart from each other in the first direction,
• the plurality of source electrodes and the plurality of drain electrodes extending in a direction perpendicular to the upper surface of the substrate through the plurality of insulation layers and the plurality of cell layers alternately stacked, wherein
• each channel layer, in the plurality of channel structures of each of the plurality of cell layers, has a corresponding one of the plurality of source electrodes and a corresponding one of the plurality of drain electrodes extending therethrough.