High selectivity isolation structure for improving effectiveness of 3d memory fabrication

A method for forming a memory device, comprising:

• forming a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate;
• etching a plurality of trenches into the plurality of word lines, defining inner sidewalls of the plurality of word lines;
• forming a ferroelectric data storage layer along the inner sidewalls of the plurality of word lines;
• forming a channel layer along the inner sidewalls of the ferroelectric data storage layer;
• forming an inner insulating layer between inner sidewalls of the channel layer and comprising a first material;
• etching the channel layer and the inner insulating layer to form an opening, wherein the opening extends continuously from an inner sidewall of the ferroelectric data storage layer to an opposing inner sidewall of the ferroelectric data storage layer;
• forming an isolation structure into the opening, wherein the isolation structure comprises a second material that is highly etching selective to the first material, and a first pair of opposing sidewalls that laterally extend past opposing outer sidewalls of the inner insulating layer;
• and
• etching the inner insulating layer and forming a pair of source/drain contacts on opposing sides of the isolation structure.

A memory device, comprising:

• a semiconductor substrate;
• a plurality of word line stacks respectively comprising word lines and insulating layers alternatingly stacked over the semiconductor substrate, the word lines extending generally in a first direction and in parallel with an upper surface of the semiconductor substrate;
• a ferroelectric data storage layer extending in the first direction along opposing inner sidewalls of the word line stacks;
• a channel layer extending in the first direction, disposed along opposing inner sidewalls of the ferroelectric data storage layer;
• a pair of source/drain regions disposed between opposing inner sides of the channel layer and extending generally perpendicular to the upper surface of the semiconductor substrate and generally perpendicular to the word lines, the pair of source/drain regions separated from one another by an insulating structure of a first dielectric material along the first direction;
• and
• an isolation structure disposed on ends of the channel layer and the pair of source/drain regions and arranged between opposing sidewalls of the ferroelectric data storage layer, wherein the isolation structure comprises a second dielectric material different from the first dielectric material.