US 2022/0285385 A1 · MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Abstract

A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stack disposed on the substrate, wherein the stack includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction; a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction; and a memory layer disposed between the channel layer and the second conductive layer.

Claims20

Dependent claims

A memory device, comprising:

a substrate having an upper surface;
a stack disposed on the substrate, wherein the stack comprises a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction;
a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction;
and
a memory layer disposed between the channel layer and the second conductive layer.

2 more elements

A method for fabricating a memory device, comprising:

providing a substrate, wherein the substrate has an upper surface;
forming a laminated body on the substrate, wherein the laminated body comprises a first insulating layer, a first conductive layer, a second insulating layer, a sacrificial layer and a third insulating layer along a first direction;
forming a first opening penetrating the laminated body;
forming a channel layer in the first opening, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction;
removing the sacrificial layer;
forming a second conductive layer at a position where the sacrificial layer is removed;
and
forming a memory layer disposed between the channel layer and the second conductive layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/190,576Filed 3 Mar 2021

Published

8 Sep 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 64/037
Of data-storage electrodes: comprising charge-trapping insulators
H10D 30/693
IGFETs having charge trapping gate insulators, e.g. MNOS transistors: vertical IGFETs having charge trapping gate insulators
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps

Memory device and method for fabricating the same

Life of this patent

Memory device and method for fabricating the same

Life of this patent

Abstract

Claims20