Integrated circuit structure and method of forming the same

A structure, comprising:

• a semiconductor substrate;
• a contact over the semiconductor substrate;
• a first dielectric layer laterally surrounding the contact;
• a second dielectric layer over the first dielectric layer and having a trench therein to expose the contact;
• a bottom electrode layer lining a sidewall of the trench and a top surface of the contact;
• a ferroelectric layer conformally formed on the bottom electrode layer;
• and
• a top electrode layer over the ferroelectric layer.

A method, comprising:

• forming a gate structure on a substrate;
• forming a source/drain feature adjacent to the gate structure;
• forming a first dielectric layer over the gate structure and the source/drain feature;
• forming a source/drain contact extending through the first dielectric layer and landing on the source/drain feature;
• forming a second dielectric layer over the first dielectric layer;
• forming a bottom electrode layer through the second dielectric layer and in contact with the source/drain contact;
• forming a ferroelectric layer over the bottom electrode layer;
• forming a top electrode layer over the ferroelectric layer;
• and
• performing an annealing process on the ferroelectric layer at a temperature higher than about 400° C.