Semiconductor memory device and method of manufacturing the semiconductor memory device

A method of manufacturing a semiconductor memory device, forming a stacked body that is penetrated by lower channel portions;

• forming upper channel portions that overlap the lower channel portions;
• forming gate insulating layers that enclose sidewalls of the upper channel portions;
• forming first gate patterns that enclose sidewalls of the gate insulating layers and that are arranged in a plurality of rows;
• forming a separation insulating pattern between a first row of the first gate patterns and a second row of the first gate patterns;
• forming a conductive layer that fills a space between the first gate patterns;
• and
• forming second gate patterns that are separated from each other by etching the conductive layer so that the separation insulating pattern is exposed.

A semiconductor memory device, comprising:

• a stacked body including conductive patterns and interlayer insulating layers that are alternately stacked;
• a lower channel portion passing through the stacked body;
• a memory layer disposed between the stacked body and the lower channel portion;
• an upper channel portion disposed on the lower channel portion;
• a gate insulating layer enclosing a sidewall of the upper channel portion;
• a first gate pattern enclosing a sidewall of the gate insulating layer;
• a separation insulating pattern contacting a first portion of the first gate pattern;
• and
• a second gate pattern contacting a second portion of the first gate pattern.

A semiconductor memory device, comprising:

• a separation insulating pattern including a first surface and a second surface that face in opposite directions;
• a first groove formed in the first surface of the separation insulating pattern;
• a second groove formed in the second surface of the separation insulating pattern;
• a first line-shaped gate pattern contacting the first surface of the separation insulating pattern and including a third groove that faces the first groove;
• a second line-shaped gate pattern contacting the second surface of the separation insulating pattern and including a fourth groove that faces the second groove;
• a first tubular gate pattern extending along a surface of the first groove and a surface of the third groove;
• a second tubular gate pattern extending along a surface of the second groove and a surface of the fourth groove;
• channel portions inserted into central areas of the first and second tubular gate patterns;
• and
• a gate insulating layer disposed between each of the first and second tubular gate patterns and each of the channel portions,

The semiconductor memory device according to clam 32, further comprising:

• lower channel portions disposed under the channel portions;
• a stacked body including interlayer insulating layers and word lines that enclose the lower channel portions and that are alternately disposed in a longitudinal direction of each of the lower channel portions;
• and
• a memory layer disposed between each of the lower channel portions and the stacked body.