Semiconductor memory device and method of manufacturing semiconductor memory device

A semiconductor memory device, comprising:

• a first stack;
• a second stack provided above the first stack and having conductive layers and insulation layers, each conductive layer and each insulation layer being alternately stacked and extending in a first direction;
• and
• a pillar provided through the second stack in a second direction intersecting the first direction,
• wherein the first stack including
• a first polycrystalline semiconductor layer having a first average crystal grain size,
• a second polycrystalline semiconductor layer having a second average crystal grain size smaller than the first average crystal grain size,
• a first intermediate layer provided between the first and second polycrystalline semiconductor layers,
• a third polycrystalline semiconductor layer having a third average crystal grain size,
• a fourth polycrystalline semiconductor layer having a fourth average crystal grain size,
• a fifth polycrystalline semiconductor layer having a fifth average crystal grain size smaller than the fourth average crystal grain size, and
• a second intermediate layer provided between the fourth and fifth polycrystalline semiconductor layers,
• the pillar including
• a semiconductor layer provided through the second stack in the second direction, and provided on the third polycrystalline semiconductor layer, and
• a charge storage layer provided between the semiconductor layer and at least one conductive layer selected from the group consisting of the conductive layers in the first direction,
• the third polycrystalline semiconductor layer being provided between the second and fifth polycrystalline semiconductor layers, and being provided on the second and fifth polycrystalline semiconductor layers, and
• the third average crystal grain size being smaller than the first average crystal grain size, and being smaller than the fourth average crystal grain size.

A method of manufacturing a semiconductor memory device, comprising:

• forming a first stack, the first stack including
• a first polycrystalline semiconductor layer having a first average crystal grain size,
• a second polycrystalline semiconductor layer having a second average crystal grain size smaller than the first average crystal grain size,
• a first intermediate layer between the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer, and
• a first sacrificial layer provided on the second polycrystalline semiconductor layer;
• alternately stacking an insulation layer and a second sacrificial layer above the first stack to form a second stack, the insulation layer and the second sacrificial layer extending in a first direction, and the second stack including a plurality of the insulation layers and a plurality of the second sacrificial layers;
• forming a pillar, the pillar including
• a semiconductor layer provided through the second stack in a second direction intersecting the first direction, and
• a memory layer provided between the semiconductor layer and at least one second sacrificial layer selected from the group consisting of the second sacrificial layers, in the first direction;
• removing the first sacrificial layer so as to expose the semiconductor layer to form a first space;
• forming a third polycrystalline semiconductor layer, the third polycrystalline semiconductor layer having a third average crystal grain size smaller than the first average crystal grain size in the first space;
• removing the second sacrificial layer to form a second space;
• and
• forming a conductive layer in the second space.