Memory Device with Improved Margin and Performance and Methods of Formation Thereof

A method comprising:

• forming a semiconductor layer stack over a semiconductor substrate, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers, a first portion of the semiconductor layer stack is in a first transistor region, a second portion of the semiconductor layer stack is in a second transistor region, and the first portion of the semiconductor layer stack and the second portion of the semiconductor layer stack have a first number of the first semiconductor layers;
• forming a patterned mask layer over the semiconductor layer stack, wherein the patterned mask layer covers the first portion of the semiconductor layer stack and exposes the second portion of the semiconductor layer stack;
• etching the exposed second portion of the semiconductor layer stack to recess the second portion of the semiconductor layer stack, wherein the recessed second portion of the semiconductor layer stack has a second number of the first semiconductor layers that is less than the first number of the first semiconductor layers;
• forming a third semiconductor layer over the recessed second portion of the semiconductor layer stack;
• and
• processing the semiconductor layer stack to form a first transistor having the first number of the first semiconductor layers in the first transistor region and a second transistor having the second number of the first semiconductor layers in the second transistor region, wherein the processing includes removing the second semiconductor layers and removing the third semiconductor layer.

A method comprising:

• forming a first transistor having a first channel stack having first channel layers over a substrate and extending along a first direction between first epitaxial source/drain features, wherein the first channel stack has a first number of the first channel layers, the first channel layers have a first channel dimension along a second direction that is different than the first direction, the first epitaxial source/drain features have a first source/drain dimension along the second direction, and the first epitaxial source/drain features have a first volume;
• forming a second transistor having a second channel stack having second channel layers over the substrate and extending along the first direction between second epitaxial source/drain features, wherein the second channel stack has a second number of the second channel layers, the second channel layers have a second channel dimension along the second direction, the second epitaxial source/drain features have a second source/drain dimension along the second direction, and the second epitaxial source/drain features have a second volume;
• and
• wherein the first number is greater than the second number, the first channel dimension is about equal to the second channel dimension, the first source/drain dimension is greater than the second source/drain dimension, and the first volume is greater than the second volume.