US 2022/0285356 A1Published application

Semiconductor memory devices and methods of fabricating the same

AssigneeSamsung Electronics Co., Ltd.

InventorYONG-HOON SON

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Abstract

Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate;
a semiconductor pattern on the substrate and extending in a first direction that is parallel to a top surface of the substrate, the semiconductor pattern including a first outer side surface, a second outer side surface that is opposite the first outer side surface, and an inner side surface between the first outer side surface and the second outer side surface;
a bit line on the first outer side surface of the semiconductor pattern and extending in a second direction that is parallel to the top surface of the substrate and is perpendicular to the first direction;
a capacitor lower electrode on the second outer side surface of the semiconductor pattern and extending in the first direction;
a gate electrode between the bit line and the capacitor lower electrode, the gate electrode including a first portion that is on a bottom surface of the semiconductor pattern, a second portion that is on a top surface of the semiconductor pattern, and a third portion that is on the inner side surface of the semiconductor pattern and extends in a third direction that is perpendicular to the top surface of the substrate;
and
a gate dielectric layer between the semiconductor pattern and the gate electrode,
wherein the gate dielectric layer is on the top surface, the bottom surface, and the inner side surface of the semiconductor pattern, and
the third portion of the gate electrode contacts the first portion and the second portion of the gate electrode.

6 more elements

A semiconductor device comprising:

a substrate;
a first insulating layer on the substrate;
a first horizontal gate pattern on the first insulating layer;
a first semiconductor pattern on the first horizontal gate pattern, the first semiconductor pattern including a first end, a second end opposite the first end, and a first channel region between the first end and the second end;
a second horizontal gate pattern on the first semiconductor pattern;
a second insulating layer on the second horizontal gate pattern;
a third horizontal gate pattern on the second insulating layer;
a second semiconductor pattern on the third horizontal gate pattern, the second semiconductor pattern including a third end, a fourth end opposite the third end, and a second channel region between the third end and the fourth end;
a fourth horizontal gate pattern on the second semiconductor pattern;
a third insulating layer on the fourth horizontal gate pattern;
a vertical gate pattern passing through the first semiconductor pattern and the second semiconductor pattern;
a first bit line between the first insulating layer and the second insulating layer and connected to the first end of the first semiconductor pattern;
a second bit line between the second insulating layer and the third insulating layer and. connected to the third end of the second semiconductor pattern;
a first capacitor lower electrode between the first insulating layer and the second insulating layer and connected to the second end of the first semiconductor pattern;
and
a second capacitor lower electrode between the second insulating layer and the third insulating layer and connected to the fourth end of the second semiconductor pattern,
wherein the vertical gate pattern contacts the first to fourth horizontal gate patterns.

14 more elements

A semiconductor device comprising:

a substrate;
a first semiconductor pattern on the substrate and extending in a first direction that is parallel to a top surface of the substrate, the first semiconductor pattern including a first end, a second end opposite the first end, and a first channel region between the first end and the second end;
a second semiconductor pattern extending in the first direction and spaced apart from the first semiconductor pattern in a second direction that is parallel to the top surface of the substrate and is perpendicular to the first direction, the second semiconductor pattern including a third end, a fourth end opposite the third end, and a second channel region between the third end and the fourth end;
an insulating layer on the substrate and between the first semiconductor pattern and the second semiconductor pattern;
a bit line extending in the second direction and connected to the first end of the first semiconductor pattern and the third end of the second semiconductor pattern;
a first capacitor lower electrode extending in the first direction and connected to the second end of the first semiconductor pattern;
a second capacitor lower electrode extending in the first direction and connected to the fourth end of the second semiconductor pattern;
a first gate electrode adjacent to the first channel region of the first semiconductor pattern;
and
a second gate electrode adjacent to the second channel region of the second semiconductor pattern,
wherein the first gate electrode includes:
a first portion on a bottom surface of the first semiconductor pattern;
a second portion on a top surface of the first semiconductor pattern;
and
a third portion passing through the first semiconductor pattern and extending in a third direction that is perpendicular to the top surface of the substrate, and
wherein the third portion of the first gate electrode contacts the first portion and the second portion of the first gate electrode.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/752,921Filed 25 May 2022
Priority: KR 10-2019-01248818 Oct 2019
Published: 8 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/03
For one transistor one-capacitor [1T-1C] memory cells: making the capacitor or connections thereto
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 12/482
Data lines or contacts therefor: bit lines

Family

Application17/035,843Continuation · filed 29 Sep 2020
Application17/752,921Continuation
US 11,374,008 B2Related patent
US 11,950,405 B2Related patent
US 2021/0104527 A1Published application
US 2022/0285356 A1This patent

From the US filing history. Foreign family members aren’t listed.

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