US 2022/0285352 A1Published application

Memory and method for manufacturing memory

AssigneeChangxin Memory Technologies, Inc.

InventorTao CHEN

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Abstract

A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.

Claims18

Dependent claims

A memory, comprising a substrate, wherein an isolation layer is disposed on the substrate, a plurality of active regions arranged in an array according to rows and columns are disposed in the isolation layer, and a plurality of word lines are formed in the plurality of active regions and the isolation layer;

and
wherein the plurality of word lines are arranged along a row direction of the plurality of active regions, each word line is in an S shape, the each word line comprises a plurality of gates disposed in the plurality of active regions and word line structures disposed in the isolation layer, the each word line is constituted by successive connection of the plurality of gates and the word line structures arranged at intervals, and the plurality of gates comprised in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.

A method for manufacturing memory, comprising:

providing a substrate;
forming an isolation layer on the substrate;
forming, in the isolation layer, a plurality of active regions arranged in an array according to rows and columns;
and
forming a plurality of word lines in the isolation layer and the plurality of active regions, wherein the plurality of word lines are arranged along a row direction of the plurality of active regions, each word line is an S shape, the each word line comprises a plurality of gates disposed in the plurality of active regions and word line structures disposed in the isolation layer, the each word line is constituted by successive connection of the plurality of gates and the word line structures arranged at intervals, and the plurality of gates comprised in the each word line are located in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are located in two correspondingly adjacent rows of active regions.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/447,198Filed 8 Sep 2021
Priority: CN 202110241856.84 Mar 2021
Published: 8 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/482
Data lines or contacts therefor: bit lines
H10B 12/485
Data lines or contacts therefor: bit line contacts

Family

Application17/447,198Continuation
US 12,213,300 B2Related patent
US 2022/0285352 A1This patent

From the US filing history. Foreign family members aren’t listed.

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