Memory Cell and Method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Han-Jong Chia, Sai-Hooi Yeong, Chi On Chui, Yu-Ming Lin
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Han-Jong Chia, Sai-Hooi Yeong, Chi On Chui, Yu-Ming Lin
Estimating the term…
An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.