Integration of multiple fin stuctures on a single substrate

A method for forming an integrated chip, the method comprising:

• forming a first plurality of semiconductor layers and a second plurality of semiconductor layers over a semiconductor substrate;
• performing a first patterning process on the first plurality of semiconductor layers, the second plurality of semiconductor layers, and the semiconductor substrate to define a first fin structure laterally adjacent to a second fin structure, wherein the first patterning process removes more of the semiconductor substrate in a first region adjacent to a sidewall of the first fin structure than in a second region adjacent to a sidewall of the second fin structure;
• forming a first gate structure that continuously extends from the first fin structure to the second fin structure;
• forming a first pair of source/drain structures on the first fin structure and on opposite sides of the first gate structure;
• forming a second pair of source/drain structure on the second fin structure and on opposite sides of the first gate structure;
• removing the first gate structure and the first plurality of semiconductor layers, thereby defining a plurality of nanostructures over the first fin structure;
• and
• forming a gate electrode that continuously extends from the plurality of nanostructures to around sidewalls of the second fin structure.

A method for forming an integrated chip (IC), the method comprising:

• forming a stack of semiconductor layers over a semiconductor substrate, wherein the stack of semiconductor layers comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers;
• forming a masking structure over the stack of semiconductor layers and the semiconductor substrate, wherein the masking structure comprises a plurality of masking layers;
• forming a plurality of mandrel structures over the masking structure, wherein the plurality of mandrel structures includes a first mandrel structure that overlies the stack of semiconductor layers and a second mandrel structure that is laterally offset from the stack of semiconductor layers by a non-zero distance;
• forming a first sidewall spacer structure along opposing sidewalls of the first mandrel structure and a second sidewall spacer structure along opposing sidewalls of the second mandrel structure;
• forming a first protection layer over the second mandrel structure;
• performing a first patterning process according to the first protection layer to remove the first sidewall spacer;
• forming a second protection layer over the first mandrel structure;
• performing a second patterning process according to the second protection layer to remove the second mandrel structure;
• performing a third patterning process according to the first mandrel structure and the second sidewall spacer to remove portions of the masking structure, thereby defining a first stack of masking layers over the stack of semiconductor layers with a first width and a second stack of masking layers laterally offset from the stack of semiconductor layers with a second width less than the first width;
• and
• performing a third patterning process on the semiconductor substrate and the stack of semiconductor layers according to the first and second stack of masking layers, thereby defining a first fin structure laterally adjacent to a second fin structure, wherein the first fin structure has the first width and the second fin structure has the second width, and wherein the stack of semiconductor layers directly overlies the first fin structure.