Deep trench via for three-dimensional integrated circuit

An integrated circuit (IC) die comprising:

• a logic layer including a transistor array with a plurality of fins of semiconductor material;
• a deep trench via in the logic layer to electrically couple a first interconnect on a first side of the logic layer with a second interconnect on a second side of the logic layer, wherein the second side is opposite the first side, and wherein the deep trench via includes a conductive material in a diffusion region or a gate region of a dummy transistor of the transistor array;
• and
• a sidewall spacer between the conductive material in the diffusion region or the gate region of the dummy transistor and an adjacent gate region or diffusion region.

A computer system comprising:

• a circuit board;
• a first integrated circuit (IC) die having a first side and a second side, wherein the first side is coupled to the circuit board, and wherein the first IC die includes:
• a logic layer including a transistor array with a plurality of fins of semiconductor material to form a plurality of logic transistors;
• a first interconnect toward the first side from the logic layer;
• a second interconnect toward the second side from the logic layer;
• and
• a deep trench via in the logic layer to electrically couple the first interconnect with the second interconnect, wherein the deep trench via is in a diffusion region or a gate region of a dummy transistor in the transistor array.
• a second IC die coupled to the second side of the IC die, wherein the second IC die is conductively coupled to another device on the circuit board via the second interconnect, the deep trench via, and the first interconnect.