High esd immunity field-effect device and manufacturing method thereof

An electrostatic discharge (ESD) protection device comprising:

• a plurality of transistors formed on a semiconductor substrate during a front-end-of-line (FEOL) process;
• metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors;
• and
• through substrate resistive components connected to drain terminals of the plurality of transistors through the metal interconnects,
• wherein the through substrate resistive components are configured to clamp an ESD voltage during an ESD event.

A method of forming an electrostatic discharge (ESD) protection device comprising:

• forming a field effect transistor on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process;
• forming a metal interconnect layer on top of the FEOL layer during a back-end-of-line (BEOL) process,
• wherein the metal interconnect layer is configured to interconnect the FET to a plurality of components formed on the semiconductor substrate;
• forming a power delivery network (PDN) under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process;
• and
• forming a through substrate resistive component between the FEOL layer and a B-BEOL layer,
• wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and a second contact of the through substrate resistive component is connected, through the PDN, to a power supply rail.