Semiconductor device and semiconductor storage device

A semiconductor device comprising:

• a substrate;
• a plurality of electrode layers provided above the substrate, and separated from each other in a first direction perpendicular to a surface of the substrate;
• a first plug provided in the plurality of electrode layers;
• first and second diffusion layers provided in the substrate, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit;
• a second plug extending in the first direction, provided at a position that does not overlap with the first diffusion layer in planar view, and electrically connected with the first diffusion layer;
• and
• a third plug extending in the first direction, and electrically connected with the second diffusion layer.

A semiconductor storage device comprising:

• a substrate;
• a plurality of electrode layers provided above the substrate, and separated from each other in a first direction perpendicular to a surface of the substrate;
• a first plug provided in the plurality of electrode layers;
• first and second diffusion layers provided in the substrate, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit;
• a lower interconnect provided above the substrate;
• a second plug extending in the first direction, provided at a position that does not overlap with the first diffusion layer in planar view, and electrically connected with the first diffusion layer via the lower interconnect;
• a source line provided above the lower interconnect;
• a first electrode layer included in the plurality of electrode layers, and provided above the source layer;
• a second electrode layer included in the plurality of electrode layers, and provided above the first electrode layer;
• a bit line provided above the second electrode layer;
• an upper interconnect provided above the bit line and the second plug;
• a semiconductor layer penetrating through the first and second electrode layers, and electrically connected with the source line and the bit line;
• a first charge storage layer provided at a position where the first electrode layer crosses the semiconductor layer;
• and
• a second charge storage layer provided at a position where the second electrode layer crosses the semiconductor layer.