Semiconductor package including redistribution substrate

A semiconductor package, comprising:

• a lower redistribution substrate;
• a first lower semiconductor chip mounted on a top surface of the lower redistribution substrate;
• a plurality of first lower solder patterns disposed between the lower redistribution substrate and the first lower semiconductor chip;
• a second lower semiconductor chip mounted on the top surface of the lower redistribution substrate;
• a plurality of second lower solder patterns disposed between the lower redistribution substrate and the second lower semiconductor chip;
• a conductive structure disposed on the top surface of the lower redistribution substrate;
• a lower molding layer disposed on the top surface of the lower redistribution substrate, the lower molding layer at least partially covering a top surface of the first lower semiconductor chip and a top surface of the second lower semiconductor chip;
• an upper redistribution substrate disposed on the lower molding layer and the conductive structure, the upper redistribution substrate being electrically connected to the conductive structure;
• a first upper semiconductor chip mounted on the upper redistribution substrate;
• a plurality of first upper solder patterns disposed between the upper redistribution substrate and the first upper semiconductor chip;
• a second upper semiconductor chip mounted on the upper redistribution substrate and laterally spaced apart from the first upper semiconductor chip;
• a plurality of second upper solder patterns disposed between the upper redistribution substrate and the second upper semiconductor chip;
• and
• an upper molding layer disposed on a top surface of the upper redistribution substrate, the upper molding layer at least partially covering a sidewall of the first upper semiconductor chip and a sidewall of the second upper semiconductor chip,
• wherein the lower molding layer extends onto a bottom surface of the first lower semiconductor chip and a bottom surface of the second lower semiconductor chip and encapsulates the plurality of first lower solder patterns and the plurality of second lower solder patterns,
• wherein the upper molding layer extends onto a bottom surface of the first upper semiconductor chip and a bottom surface of the second upper semiconductor chip and encapsulates the plurality of first upper solder patterns and the plurality of second upper solder patterns,
• wherein the conductive structure is disposed between the first lower semiconductor chip and the second lower semiconductor chip,
• wherein the lower redistribution substrate includes:
• a lower dielectric layer;
• a redistribution pattern disposed in the lower dielectric layer, the redistribution pattern including a via portion and a wire portion;
• and
• a seed pattern disposed on a bottom surface of the redistribution pattern, and
• wherein the upper redistribution substrate includes:
• an upper dielectric layer;
• a redistribution layer disposed in the upper dielectric layer, the redistribution layer including a via pattern and a wire pattern;
• and
• an upper seed pattern disposed on a bottom surface of the redistribution layer.

A semiconductor package, comprising:

• a lower redistribution substrate;
• a lower semiconductor chip mounted on a top surface of the lower redistribution substrate;
• a plurality of lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip;
• a plurality of conductive structures disposed on the top surface of the lower redistribution substrate;
• a lower molding layer disposed on the top surface of the lower redistribution substrate, the lower molding layer at least partially covering a top surface of the lower semiconductor chip;
• an upper redistribution substrate disposed on the lower molding layer and the plurality of conductive structures, the upper redistribution substrate being electrically connected to the plurality of conductive structures;
• an upper semiconductor chip mounted on a top surface of the upper redistribution substrate;
• a plurality of upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip;
• and
• an upper molding layer disposed on the top surface of the upper redistribution substrate, the upper molding layer at least partially covering a sidewall of the upper semiconductor chip,
• wherein the lower molding layer extends between the lower redistribution substrate and the lower semiconductor chip and encapsulates the plurality of lower solder patterns,
• wherein the upper molding layer extends between the upper redistribution substrate and the upper semiconductor chip and encapsulates the plurality of upper solder patterns,
• wherein the number of the plurality of conductive structures is the same as or greater than the number of a plurality of upper chip pads of the upper semiconductor chip,
• wherein the lower redistribution substrate includes:
• a redistribution pattern disposed in a lower dielectric layer, the redistribution pattern including a via portion and a wire portion;
• and
• a seed pattern disposed on a bottom surface of the redistribution pattern, and
• wherein the upper redistribution substrate includes:
• a redistribution layer disposed in an upper dielectric layer, the redistribution layer including a via pattern and a wire pattern;
• and
• a seed layer disposed on a bottom surface of the redistribution layer.