Semiconductor device with edge-protecting spacers over bonding pad

A semiconductor device, comprising:

• a bonding pad disposed over a semiconductor substrate;
• a first spacer disposed over a top surface of the bonding pad;
• a dielectric liner disposed between the first spacer and the bonding pad;
• a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide;
• a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad;
• a second spacer disposed over a sidewall of the bonding pad;
• a first passivation layer covering the second spacer, wherein the first spacer is in direct contact with the first passivation layer;
• and
• a second passivation layer between the first passivation layer and the bonding pad, wherein the second spacer is covered by the second passivation layer, and a portion of the conductive bump is surrounded by the first passivation layer and the second passivation layer.