Semiconductor packages and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShau-Lin SHUE, Shin-Yi YANG, Ming-Han LEE
Life of this patent
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Abstract
Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.
Claims20
A semiconductor device, comprising:
- a first integrated circuit die comprising a first sealing ring encircling a first circuit region;
- a second integrated circuit die comprising a second sealing ring encircling a second circuit region;
- a dielectric layer formed between the first sealing ring and the second sealing ring;
- and
- a conductive line extending from the first circuit region to the second circuit region through the first sealing ring, the dielectric layer, and the second sealing ring.
An integrated circuit die, comprising:
- a device layer comprising one or more semiconductor devices;
- an interconnect structure formed on the device layer, wherein the interconnect structure comprises:
- a dielectric layer;
- a sealing ring formed in the dielectric layer encircling a circuit region within the dielectric layer;
- and
- one or more conductive features embedded in the circuit region of the dielectric layer, wherein the one or more conductive features are connected to one or more semiconductor devices in the device layer;
- and
- a plurality of edge interconnect features formed in the dielectric layer, wherein the plurality of edge interconnect features extending outwards from the circuit region through the sealing ring.
A method for forming a semiconductor device, comprising:
- forming a first integrated circuit die having a first edge interconnect feature, and a second integrated circuit die having a second edge interconnect feature on a substrate, wherein a scribe line is formed between the first and second integrated circuit dies, and the first edge interconnect feature connected to the second edge interconnect feature in the scribe line;
- and
- attaching the first and second integrated circuit dies to a printed circuit board with the first and second circuit dies remaining connected to each other at the scribe line.
Dependencies are inferred from the claim text.