Package substrate and semiconductor package including the same

A package substrate comprising:

• an insulation substrate;
• a conductive layer provided in the insulation substrate;
• upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer;
• lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer;
• and
• trenches provided at portions of the insulation substrate adjacent to corner pads among the upper pads, the corner pads being provided at corners of the insulation substrate in a direction crossing a direction from a central portion of the insulation substrate to the corners of the insulation substrate, a depth of each of the trenches being from 5% to 100% of a depth of the insulation substrate,
• wherein at least one of the trenches has an arc shape in at least one row, a plurality of dots shape, or a zigzag shape that partially surround each of the upper pads.

A semiconductor package comprising:

• a semiconductor chip comprising bump pads;
• conductive bumps connected to the bump pads, respectively;
• and
• a package substrate comprising:
• an insulation substrate provided under the semiconductor chip,
• a conductive layer provided in the insulation substrate,
• upper pads provided on an upper surface of the insulation substrate and electrically connecting the conductive layer with the conductive bumps,
• lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and
• at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads,
• wherein the at least one trench has an arc shape in at least one row, a plurality of dots shape, or a zigzag shape that partially surround each of the upper pads.