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US 2022/0285285 A1Published application
Memory device and method of manufacturing the same
AssigneeSK hynix Inc.
InventorYoo Hyun NOH
Life of this patent
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Abstract
The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns.
Claims20
A memory device comprising:
- a main chip region;
- a chip guard region disposed adjacent to the main chip region;
- a plurality of chip guard patterns formed in the chip guard region;
- and
- a buffer slit formed in a space between the plurality of chip guard patterns.
2 more elements
A method of manufacturing a memory device, the method comprising:
- forming a stack in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked on a substrate in a main chip region, a scribe region, and a chip guard region between the main chip region and the scribe region;
- forming a plurality of trenches that pass through the stack in the chip guard region;
- forming sacrificial patterns in the plurality of trenches;
- forming a slit that passes through the stack in a space between the plurality of trenches;
- removing the sacrificial layers that are exposed through the slit and forming a plurality of plate electrodes in a space from which the sacrificial layers are removed;
- removing the sacrificial patterns and forming chip guard patterns in a space from which the sacrificial patterns are removed;
- and
- forming a buffer slit in the slit.
5 more elements
A method of manufacturing a memory device, the method comprising:
- forming a stack in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked on a substrate in a main chip region and a chip guard region;
- forming a plurality of trenches that pass through the stack in the chip guard region;
- forming sacrificial patterns in the plurality of trenches;
- forming a plurality of first slits that pass through the stack on the main chip region and forming a second slit that passes through the stack in a space between the plurality of trenches;
- removing the sacrificial layers that are exposed through the first slits and the second slits and then forming a plurality of plate electrodes in a space from which the sacrificial layers are removed;
- forming a plurality of chip guard patterns by filling each of the plurality of trenches with a conductive material after removing the sacrificial patterns;
- and
- forming a buffer slit in the second slit.
5 more elements
Dependencies are inferred from the claim text.