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US 2022/0285273 A1Published application
High Density 3D Interconnect Configuration
AssigneeApple Inc.
InventorsSanjay Dabral, Zhitao Cao, Kunzhong Hu, Jun Zhai
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Abstract
Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.
Claims21
(canceled)
An electronic system comprising:
- a circuit board;
- a die bonded to the circuit board with a plurality of solder bumps;
- a chiplet directly underneath the die and laterally adjacent the plurality of solder bumps, wherein the chiplet includes:
- a bulk silicon layer;
- a plurality of trench capacitors in the bulk silicon layer, and a thorough silicon via through the bulk silicon layer;
- a build-up layer including positive supply (Vdd) routing and negative supply (Vss) routing;
- and
- a backside metal layer, wherein the back side metal layer is bonded to the circuit board with a conductive bump.
5 more elements
Dependencies are inferred from the claim text.