Novel self-aligned via structure by selective deposition
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
Estimating the term…
In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.
A semiconductor device comprising one or more multilayer interconnections, comprising:
A method of forming a semiconductor device comprising:
A method of forming a semiconductor device comprising:
Dependencies are inferred from the claim text.