Semiconductor device

A semiconductor device, comprising:

• a semiconductor substrate;
• a first pattern on the semiconductor substrate;
• a second pattern disposed at substantially the same level as the first pattern and spaced apart from the first pattern;
• peripheral circuit on the semiconductor substrate, at least a portion of the peripheral circuit being between the semiconductor substrate and the first pattern;
• a dummy interconnection structure on the semiconductor substrate;
• a stacked structure including cell gate conductive patterns on the first pattern, the cell gate conductive patterns being stacked while being spaced apart from web other in vertical direction perpendicular to an upper surface of the first pattern;
• a cell vertical structure disposed on the first pattern, passing through the cell gate conductive patterns, and directly contacting the first pattern;
• and
• a dummy contact plug directly contacting the second pattern,
• wherein an upper end of the dummy contact plug is at a higher level than an uppermost cell gate conductive pattern among the cell Mate conductive patterns,
• wherein a lower end of the dummy contact plug is at a lower level than a lowermost cell gate conductive pattern among the cell gate conductive patterns,
• wherein at least one side of the stacked structure has a staircase shape,
• wherein the dummy interconnection structure is electrically isolated,
• wherein the dummy interconnection structure includes at least three dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate,
• wherein the at least three dummy patterns include:
• a dummy gate pattern;
• a first dummy pattern disposed at a higher level than the dummy gate pattern;
• and
• a second dummy pattern disposed at a higher level than the first dummy pattern, and
• wherein the peripheral circuit includes:
• a peripheral gate disposed at substantially the same level as the dummy gate pattern;
• a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern;
• and
• a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern.

An electronic system, comprising:

• a memory device;
• and
• a processor to control the memory device,
• wherein the memory device comprises:
• a semiconductor substrate;
• a first pattern on the semiconductor substrate;
• a second pattern disposed at substantially the same level as the first pattern and spaced apart from the second pattern;
• a peripheral circuit on the semiconductor substrate, at least a portion of the peripheral circuit being between the semiconductor substrate and the first pattern;
• a dummy interconnection structure on the semiconductor substrate;
• a stacked structure including cell gate conductive patterns on the first pattern, the cell gate conductive patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the first pattern;
• a cell vertical structure disposed on the first pattern, passing through the cell gate conductive patterns, and directly contacting the first pattern;
• and
• a dummy contact plug directly contacting the second pattern,
• wherein an upper end of the dummy contact plug is at a higher level than an uppermost cell gate conductive pattern among the cell gate conductive patterns,
• wherein a lower end of the dummy contact plug, is at a lower level than a lowermost cell gate conductive pattern among the cell gate conductive patterns,
• wherein at least one side of the stacked structure has a staircase shape,
• wherein the dummy interconnection structure is electrically isolated,
• wherein the dummy interconnection structure includes at least three dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate,
• wherein the at least three dummy patterns include:
• a dummy gate pattern;
• a first dummy pattern disposed at a higher level than the dummy gate pattern;
• and
• a second dummy pattern disposed at a higher level than the first dummy pattern, and wherein the peripheral circuit includes:
• a peripheral gate disposed at substantially the same level as the dummy gate pattern;
• a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern;
• and
• a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern.