Wafer level packaging having redistribution layer formed utilizing laser direct structuring

A method of forming a wafer-level package, the method comprising:

• singulating a wafer into a plurality of reconstituted integrated circuit dice and a plurality of dummy pillars;
• affixing a carrier to a front side of the plurality of integrated circuit dice and the plurality of dummy pillars;
• forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dice, over side edges of the plurality of integrated circuit dice, over a back side of the plurality of dummy pillars, over side edges of the plurality of dummy pillars, and over adjacent portions of the carrier;
• activating desired areas of the LDS activatable resin to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die, at least one of the conductive areas associated with each dummy pillar being formed to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that dummy pillar;
• and
• forming first conductive traces on the conductive areas formed within the LDS activatable resin by the activation.

A wafer-level package, comprising:

• an integrated circuit die having a plurality of pads on its front side;
• a resin layer surrounding edge sides of the integrated circuit die, and surrounding the front side of the integrated circuit die;
• wherein the resin layer includes an activatable catalyst material;
• a first passivation layer having its back surface in contact with a front surface of the resin layer adjacent the front side of the integrated circuit die;
• a first solder resist layer having its back surface in contact with a front surface of the passivation layer;
• and
• a redistribution layer comprising:
• first activated portions of the resin layer adjacent the plurality of pads to form electrical connections extending from the plurality of pads to the back surface of the resin layer;
• second activated portions of the resin layer extending along the back surface of the resin layer toward portions of the resin layer surrounding the edge sides of the integrated circuit die;
• third activated portions of the resin layer extending along the portions of the resin layer surrounding the edge sides of the integrated circuit die;
• and
• a first interconnect structure extending from the second activated portions of the resin layer, through the first passivation layer, and through the first solder resist layer.