US 2022/0285173 A1Published application

Electronics module and method for producing it

AssigneeRogers Germany GmbH

InventorsKarsten SCHMIDT, Andreas Meyer, Eckart Hoene, Christoph Marczok, Tina Thomas, Ruben Kahle

Life of this patent

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Abstract

Electronic module (1) including an encapsulation (20), a carrier substrate (10) enclosed by the encapsulation (20) and having a component side (25) which has a first metallization layer (15) and on which at least one first electronic component (30) is arranged, wherein at least one second metallization layer (35) for at least one second electronic component (31), in particular for controlling the first electronic component (30), is provided on an outer side (A) of the encapsulation (2), wherein the encapsulation (20) has at least one plated-through hole (5) for electrical connection, in particular for direct electrical connection, of the first electronic component (30) and the second electronic component (31).

Claims20

Dependent claims

An electronic module (1), comprising

an encapsulation (20) and
a carrier substrate (10) at least partially embedded in the encapsulation (20) and having a component side (25), which has a first metallization layer (15) and on which at least one first electronic component (30) is arranged, wherein the first electronic component (30) is enclosed by the encapsulation and the carrier substrate (10) is a metal-ceramic substrate,
wherein at least one second metallization layer (35) for at least one second electronic component (31), in particular for controlling the first electronic component (30), is provided on an outside (A) of the encapsulation (20),
wherein the encapsulation (20) has at least one through hole plating (5) for an electrical connection of the first electronic component (30) and the second electronic component (31).

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/056,282Filed 14 May 2019
Priority: DE 10 2018 111 989.518 May 2018
Published: 8 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
H10W 74/016
Manufacture or treatment: using moulds
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers

Family

US 12,575,440 B2Related patent
US 2022/0285173 A1This patent

From the US filing history. Foreign family members aren’t listed.

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