Method for forming semiconductor device structure with gate

A method for forming a semiconductor device structure, comprising:

• providing a substrate and an insulating layer over the substrate, wherein the insulating layer has a wide trench and a narrow trench, the wide trench exposes a first portion of the substrate, the narrow trench exposes a second portion of the substrate, and the wide trench is wider than the narrow trench;
• forming a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench;
• depositing a work function layer over the gate dielectric layer and in the wide trench and the narrow trench using an atomic layer deposition process, wherein a first deposition rate of the work function layer in the narrow trench is less than a second deposition rate of the work function layer in the wide trench during the atomic layer deposition process;
• forming a gate electrode layer over the work function layer;
• and
• removing the gate dielectric layer, the work function layer, and the gate electrode layer outside of the wide trench and the narrow trench.

A method for forming a semiconductor device structure, comprising:

• providing a substrate and an insulating layer over the substrate, wherein the insulating layer has a first trench and a second trench, the first trench exposes a first portion of the substrate, the second trench exposes a second portion of the substrate, and a first aspect ratio of the first trench is lower than a second aspect ratio of the second trench;
• depositing a gate dielectric layer over the insulating layer and in the first trench and the second trench using an atomic layer deposition process, wherein a first deposition rate of the gate dielectric layer over the first portion of the substrate is greater than a second deposition rate of the gate dielectric layer over the second portion of the substrate during the atomic layer deposition process;
• forming a gate electrode layer over the gate dielectric layer;
• and
• removing the gate dielectric layer and the gate electrode layer outside of the first trench and the second trench.