Method for fabricating semiconductor device

A method for fabricating a semiconductor device, the method comprising:

• forming an N-type source/drain region and a P-type source/drain region in a substrate;
• forming an interlayer insulating layer on the substrate;
• forming contact holes respectively exposing the N-type source/drain region and the P-type source/drain region by etching the interlayer insulating layer;
• exposing the N-type and P-type source/drain regions to a pre-annealing process;
• forming an N-type additional doped region by doping an N-type additional dopant in the pre-annealed N-type source/drain region;
• forming a P-type additional doped region by doping a P-type additional dopant in the pre-annealed P-type source/drain region;
• exposing the N-type and P-type additional doped regions to a post-annealing;
• and
• forming a metal silicide on each of the post-annealed N-type and P-type additional doped regions.

A method for fabricating a semiconductor device, the method comprising:

• forming an N-type source/drain region and a P-type source/drain region in a substrate;
• forming an interlayer insulating layer on the substrate;
• forming contact holes respectively exposing the N-type source/drain region and the P-type source/drain region by etching the interlayer insulating layer;
• forming an N-type additional doped region by doping an N-type additional dopant in the N-type source/drain region;
• exposing the N-type additional doped region, the N-type source/drain region, and the P-type source/drain region to a pre-annealing process;
• forming a P-type additional doped region by doping a P-type additional dopant in the pre-annealed P-type source/drain region;
• exposing the N-type and P-type additional doped regions to the post-annealing process;
• and
• forming a metal silicide on the post-annealed N-type additional doped region and the post-annealed P-type additional doped region.