Semiconductor storage device

Abstract

A semiconductor storage device includes a memory cell array includes a plurality of memory cell transistors, a plurality of word lines connected to gates of the memory cell transistors, a voltage generation circuit configured to generate a voltage applied to each of the word lines, and a control circuit configured to control an operation of the memory cell array. In a write operation for writing data to the memory cell array that includes multiple loops of a program operation and a verify operation, the control circuit controls an operation of the voltage generation circuit so that a rate of increase of a voltage applied to a non-selected word line at a beginning of the verify operation is different for at least two of the loops.

Dependencies are inferred from the claim text.