Dynamic program erase targeting with bit error rate

A method comprising:

• presetting, by a processing device to higher than a default value, a voltage level of an erase distribution of a memory array, the memory array comprising memory cells of a first logical page type and of a second logical page type;
• adjusting, multiple times, a value of at least some of a plurality of valley margins of programming distributions of the first logical page type to equalize relative valley margins of the first logical page type such that read window budgets (RWB) for valleys of the first logical page type are approximately a same RWB;
• determining a bit error rate (BER) of the memory array;
• and
• increasing the voltage level by a voltage step in response to the BER not satisfying a BER control value.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

• selecting a program targeting rule from a set of rules based on values of a plurality of valley margins of programming distributions of a memory array;
• performing, based on the program targeting rule, a program erase targeting operation to adjust a voltage level associated with an erase distribution of the memory array;
• determining a bit error rate (BER) of the memory array;
• and
• reducing the voltage level by a voltage step in response to the BER satisfying a BER control value.