Negative bit line biasing during quick pass write programming

An apparatus, comprising:

• a plurality of memory cells, each of the plurality of memory cells being connected to one of a plurality of word lines and one of a plurality of bit lines and being arranged in a plurality of blocks and configured to retain a threshold voltage corresponding to one of a plurality of data states;
• a control circuit coupled to the plurality of word lines and the plurality of bit lines and configured to:
• in a first programming loop;
• apply a first programming voltage to a control gate of a selected word line, and
• apply a first bitline voltage to a bitline coupled to a first memory cell being programmed to a first data state and to a bitline coupled to a second memory cell being programmed to a second data state, and
• in a second programming loop;
• apply a second programming voltage to a control gate of the selected word line,
• simultaneously apply a second bitline voltage to the bitline coupled to the first memory cell and apply a third bitline voltage to the bitline coupled to the second memory cell,
• the second bitline voltage being greater than the first bitline voltage to reduce a programming speed of the first memory cell and the third bitline voltage being less than the first bitline voltage to increase a programming speed of the second memory cell during the second programming loop.

A controller in communication with a memory apparatus that includes a plurality of memory cells, each of the plurality of memory cells being connected to one of a plurality of word lines and one of a plurality of bit lines and being arranged in a plurality of blocks and configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller being configured to:

• in a first programming loop;
• apply a first programming voltage to a control gate of a selected word line, and
• apply a first bitline voltage to a bitline coupled to a first memory cell being programmed to a first data state and to a bitline coupled to a second memory cell being programmed to a second data state, and
• in a second programming loop;
• apply a second programming voltage to the control gate of the selected word line,
• simultaneously apply a second bitline voltage to the bitline coupled to the first memory cell and apply a third bitline voltage to the bitline coupled to the second memory cell,
• the second bitline voltage being greater than the first bitline voltage to reduce a programming speed of the first memory cell and the third bitline voltage being less than the first bitline voltage to increase a programming speed of the second memory cell.