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US 2022/0284941 A1Published application
Power mode wake-up for memory on different power domains
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChe-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
Life of this patent
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Abstract
A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
Claims20
A memory I/O system, comprising:
- a first header circuit configured to receive a power supply voltage signal and having a first output terminal configured to provide a first output voltage signal in a first power domain;
- a first plurality of peripheral circuits connected to the first output terminal;
- a second header circuit configured to receive the power supply voltage signal and having a second output terminal configured to provide a second output voltage signal in a second power domain;
- a second plurality of peripheral circuits connected to the second output terminal;
- and
- a control switch connected between the first and second header circuits configured to selectively interconnect the first and second output terminals.
3 more elements
A power control system, comprising:
- a power supply rail configured to receive a power supply voltage signal;
- a first header circuit connected to the power supply rail and configured to selectively connect a first plurality of memory peripheral circuits to a first output voltage signal in a first power domain in a memory operation mode and disconnect the first plurality of memory peripheral circuits from the first output voltage signal in the first power domain in a sleep mode;
- a second header circuit connected to the power supply rail and configured to selectively connect a second plurality of memory peripheral circuits to a second output voltage signal in a second power domain in the memory operation mode and disconnect the second plurality of memory peripheral circuits from the second output voltage signal in the second power domain in the sleep mode;
- and
- a control switch connected between the first and second header circuits;
- wherein the first header circuit is configured to connect the first plurality of memory peripheral circuits to the first output voltage signal in the first power domain in a wake up mode, and the control switch is configured to selectively interconnect the first and second output terminals in the wake up mode.
3 more elements
A method, comprising:
- applying a power supply voltage signal to a first header circuit and a second header circuit;
- outputting a first output voltage signal in a first power domain to a first plurality of memory peripheral circuits by the first header circuit in a memory operation mode;
- outputting a second output voltage signal in a second power domain to a second plurality of memory peripheral circuits by the second header circuit;
- disconnecting the first output voltage signal in the first power domain from the first plurality of memory peripheral circuits by the first header circuit in a sleep mode;
- disconnecting the second output voltage signal in the second power domain from the second plurality of memory peripheral circuits by the second header circuit in the sleep mode;
- and thereafter,
- interconnecting output terminals of the first and second header circuits to output the first supply voltage in the first power domain to the second plurality of peripheral circuits by the first header circuit in a wake up mode.
4 more elements
Dependencies are inferred from the claim text.