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US 2022/0284940 A1Published application
Time tracking circuit for fram
AssigneeTexas Instruments Incorporated
InventorDavid J. Toops
Life of this patent
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Abstract
An example memory circuit for reading and/or writing FRAM memory includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.
Claims17
An integrated circuit device comprising:
- a capacitive memory array that includes:
- a set of bit line input/outputs;
- a set of word line inputs;
- and
- a set of plate inputs;
- a row driver circuit coupled to the set of word line inputs;
- a set of plate drive transistors coupled to the set of plate inputs, wherein each of the set of plate drive transistors has a respective delay;
- a plate driver circuit coupled to the set of plate drive transistors;
- and
- a controller coupled to the row driver circuit, the plate driver circuit, and the set of bit line input/outputs, wherein the controller is configured to perform a read operation by:
- providing a first signal to the row driver circuit configured to cause the row driver circuit to apply a first voltage to at least a subset of the set of word line inputs;
- after a first delay, providing a second signal to the plate driver circuit configured to cause the plate driver circuit to cause the set of plate drive transistors to apply a second voltage to at least a subset of the set of plate inputs such that:
- the first delay is less than a minimum amount of read delay associated with the set of plate inputs of the capacitive memory array;
- and
- a sum of the first delay and the respective delays of the set of plate drive transistors is greater than the minimum amount of read delay associated with the set of plate inputs of the capacitive memory array;
- and
- thereafter, receiving a value from the capacitive memory array via the set of bit line input/outputs.
14 more elements
An integrated circuit device comprising:
- a capacitive memory array that includes:
- a set of bit line input/outputs;
- and
- a set of word line inputs;
- and
- a set of bit line drive transistors coupled to the set of bit line input/outputs, wherein each of the set of bit line drive transistors has a respective delay;
- a bit line driver circuit coupled to the set of bit line drive transistors;
- a row driver circuit coupled to the set of word line inputs;
- and
- a controller coupled to the bit line driver circuit and the row driver circuit, wherein the controller is configured to perform a write operation by:
- providing a first signal to the row driver circuit configured to cause the row driver circuit to apply a first voltage to at least a subset of the set of word line inputs;
- and
- after a first delay, providing a second signal to the bit line driver circuit configured to cause the bit line driver circuit to cause the set of bit line drive transistors to apply a second voltage to at least a subset of the set of bit line input/outputs such that:
- the first delay is less than a minimum amount of write delay associated with the set of bit line input/outputs of the capacitive memory array;
- and
- a sum of the first delay and the respective delays of the set of bit line drive transistors is greater than the minimum amount of write delay associated with the set of bit line input/outputs of the capacitive memory array.
13 more elements
A method comprising:
- performing a read operation on a capacitive memory array that includes a set of bit line input/outputs, a set of word line inputs, and a set of plate inputs by:
- providing a first signal to a row driver circuit;
- based on the first signal, applying, using the row driver circuit, a first voltage to at least a subset of the set of word line inputs;
- providing a second signal to a plate driver circuit a first delay after the providing of the first signal;
- based on the second signal, applying, using the plate driver circuit, a second voltage to at least a subset of the set of plate inputs, wherein the first delay associated with the second signal is less than minimum amount of read delay associated with the set of plate inputs of the capacitive memory array and the applying of the second voltage is performed after the minimum amount of read delay associated with the set of plate inputs of the capacitive memory array;
- and
- receiving a value via the set of bit line input/outputs.
4 more elements
Dependencies are inferred from the claim text.