Nonvolatile memory device for performing double sensing operation

A nonvolatile memory device comprising:

• a cell string comprising a plurality of memory cells coupled in series;
• a bit line coupled to the cell string;
• and
• a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period,
• wherein the page buffer comprises:
• a first coupling unit suitable for coupling the bit line and the first sensing node in response to a first control signal;
• a second coupling unit suitable for coupling the first and second sensing nodes in response to a second control signal, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period;
• a first latch unit suitable for latching a logic level corresponding to a voltage level of the first sensing node in response to a third control signal;
• and
• a second latch unit suitable for latching a logic level corresponding to a voltage level of the second sensing node in response to a fourth control signal.