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US 2022/0284841 A1Published application
Display driving circuit including crack detector and display device including the display driving circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsJinhong Hwang, Siwoo Kim
Life of this patent
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Abstract
A display driving circuit includes a central area and a boundary area surrounding the central area. The display driving circuit includes a first crack detector circuit in the central area; and a first crack sensing line in the boundary area, wherein the first crack detector circuit is configured to detect a crack in the first crack sensing line in response to a first test command, and output a test result signal including information about a presence or an absence of a crack in the first crack sensing line.
Claims20
A nonvolatile memory device comprising:
- a first pin configured to receive a first signal from a memory controller;
- a second pin configured to receive a second signal from the memory controller;
- third pins configured to receive third signals from the memory controller;
- a fourth pin configured to receive a write enable signal from the memory controller;
- a memory cell array;
- and
- a memory interface circuit configured to obtain a command, an address, and data from the third signals in a first mode and to obtain the command and the address from the first signal and the second signal and the data from the third signals in a second mode,
- wherein the memory interface circuit is configured such that:
- in the first mode, the memory interface circuit obtains the command from the third signals received in an enable period of the first signal based on a toggle timing of the write enable signal and obtains the address from the third signals received in an enable period of the second signal based on a toggle timing of the write enable signal,
- in the second mode, the memory interface circuit obtains the command from the first signal and the second signal, received during a first time period including a predetermined number of cycle periods, based on a toggle timing of the write enable signal, according to the first signal having an enable state received in a first cycle period of the first time period;
- and obtains the address from the first signal and the second signal, received during a second time period including the predetermined number of cycle periods, based on a toggle timing of the write enable signal, according to the second signal having an enable state received in a second cycle period of the second time period.
8 more elements
A nonvolatile memory device comprising:
- a first pin configured to receive a control signal from a memory controller;
- a second pin configured to receive a write enable signal from the memory controller;
- third pins configured to receive data signals from the memory controller;
- a memory cell array;
- and
- a memory interface circuit,
- wherein, according to the control signal received during a first cycle period and a second cycle period of a time period including a predetermined number of cycle periods, the memory interface circuit is configured to obtain a command or an address from the control signal received during remaining cycle periods of the time period,
- wherein, when the control signal received during the first cycle period is in an enable state, the memory interface circuit obtains the command from the control signal received during the remaining cycle periods based on a toggle timing of the write enable signal, and
- wherein, when the control signal received during the second cycle period is in an enable state, the memory interface circuit obtains the address from the control signal received during the remaining cycle periods based on a toggle timing of the write enable signal.
6 more elements
A nonvolatile memory device comprising:
- first pins configured to receive a plurality of control signals including a first control signal and a second control signal from a memory controller;
- a second pin configured to receive a write enable signal from the memory controller;
- third pins configured to receive data signals from the memory controller;
- and
- a memory interface circuit,
- wherein the memory interface circuit obtains a command from the plurality of control signals received during a first time period including a predetermined number of cycle periods, based on a toggle timing of the write enable signal, according to the first control signal having an enable state received in a first cycle period of the first time period;
- and obtains an address from the plurality of control signals received during a second time period including the predetermined number of cycle periods, based on a toggle timing of the write enable signal, according to the second control signal having an enable state received in a second cycle period of the second time period.
4 more elements
Dependencies are inferred from the claim text.