High power rf switch with controlled well voltage for improved linearity
AssigneepSemi Corporation
InventorsDavid KOVAC, Joseph GOLAT
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Abstract
RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.
Claims18
(canceled)
A radio frequency (RF) switch comprising a field effect transistor (FET), the FET comprising a first well and a second well, wherein:
- the second well is of an opposite semiconductor polarity to the first well and a substrate of the FET;
- the FET is fabricated with a bulk complementary metal-oxide-semiconductor (CMOS) process and is configured to:
- receive a gate bias voltage switchable between a gate first bias voltage level and a gate second bias voltage level to put the FET in an ON or OFF state respectively, and
- the gate second bias voltage is negative with respect to ground.
A method of biasing a radio frequency (RF) switch comprising a field effect transistor (FET) switch, the FET switch manufactured using a bulk CMOS process, the method comprising:
- in an ON state of the FET switch:
- applying a first level shifted gate voltage to a gate terminal of the FET switch,
- applying a first level shifted first well voltage to a first well terminal of the FET switch, and
- applying a first level shifted second well voltage to a second well terminal of the FET switch;
- in an OFF state of the FET switch:
- applying a second level shifted gate voltage different from the first gate voltage to the gate terminal of the FET switch;
- applying a second level shifted first well voltage different from the first well voltage to the first well terminal of the FET switch, and
- applying, at a same time of the second level shifted first well voltage, a second level shifted well voltage different from the first well voltage to the second well terminal of the FET switch,
- wherein the second level shifted gate voltage and the second level shifted first well voltage are both negative with respect to ground.
Dependencies are inferred from the claim text.