Semiconductor device structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSai-Hooi YEONG, Chi-On CHUI, Chien-Ning YAO
Life of this patent
Estimating the term…
Abstract
A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure over the substrate, and a FeFET device over a first region of the substrate. The FeFET includes a first gate stack across the first fin structure. The semiconductor device structure also includes first gate spacer layers alongside the first gate stack, and a ferroelectric layer over the first gate stack. At least a portion of the ferroelectric layer is located between upper portions of the first gate spacer layers and is adjacent to the first gate stack.
Claims20
A semiconductor device structure, comprising:
- a substrate;
- a first fin structure over the substrate;
- and
- a ferroelectric field effect transistor (FeFET) device over a first region of the substrate, the FeFET comprising a first gate stack across the first fin structure;
- first gate spacer layers alongside the first gate stack;
- and
- a ferroelectric layer over the first gate stack, wherein at least a portion of the ferroelectric layer is located between upper portions of the first gate spacer layers and is adjacent to the first gate stack.
A semiconductor device structure, comprising:
- a first set of nanostructures over a substrate;
- a first gate stack wrapping around the first set of nanostructures;
- a first ferroelectric layer directly above the first gate stack;
- an interlayer dielectric layer surrounding the first gate stack and the first ferroelectric layer;
- and
- a via through the interlayer dielectric layer and coupling to the first ferroelectric layer.
A semiconductor device structure, comprising:
- a first active region and a second active region over a substrate;
- a first gate stack surrounding the first active region and a second gate stack surrounding the second active region;
- a first dielectric capping layer over the first gate stack;
- a ferroelectric layer over the second gate stack, wherein the first dielectric capping layer and the ferroelectric layer are made of different materials;
- a first via through the first dielectric capping layer and on the first gate stack;
- and
- a top electrode layer on the ferroelectric layer.
Dependencies are inferred from the claim text.