Silicon Carbide Transistor Device

A silicon carbide transistor device comprising:

• a silicon carbide semiconductor substrate having a top surface;
• a silicon carbide epitaxial layer formed at the top surface of the silicon carbide semiconductor substrate;
• a source structure formed in a top surface of the silicon carbide epitaxial layer, the source structure comprising a p-well region, an n-type source region and a p-type contact region;
• a source contact structure formed over and electrically connected to a top surface of the source structure, the source contact structure comprising titanium carbide, tungsten carbide, or nickel carbide;
• and
• a planar gate structure including a gate dielectric and a gate runner adjacent a p-type channel region, wherein the gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure, and wherein the gate runner is electrically insulated from the channel region, the source structure and the source contact structure by the gate dielectric, the gate runner overlapping the channel region and at least part of the source contact structure.

A method for manufacturing a silicon carbide transistor device, the method comprising:

• epitaxially forming a silicon carbide epitaxial layer over a top surface of a silicon carbide semiconductor substrate;
• forming a source structure in a top surface of the silicon carbide epitaxial layer, the source structure comprising a p-well region, a n-type source region and a p-type contact region;
• forming a source contact structure over and electrically connected to the top surface of the source structure, wherein the source contact structure comprises titanium carbide, tungsten carbide, or nickel carbide;
• and
• after the forming of the source contact structure, forming a planar gate structure that includes gate dielectric and a gate runner so that the gate dielectric covers at least part of the source structure and at least part of the source contact structure, and so that the gate runner is electrically insulated from the source structure and the source contact structure by the gate dielectric and overlaps at least part of the source contact structure.

A silicon carbide transistor device comprising:

• a silicon carbide semiconductor substrate having a top surface, wherein the silicon carbide semiconductor substrate is a 4H—SiC substrate;
• a silicon carbide epitaxial layer formed at the top surface of the silicon carbide semiconductor substrate;
• a source structure formed in a top surface of the silicon carbide epitaxial layer, the source structure comprising a p-well region, an n-type source region and a p-type contact region;
• a source contact structure formed over and electrically connected to a top surface of the source structure, the source contact structure comprising titanium carbide and having a thickness in a range of 2 nm to 200 nm;
• a drain structure formed at a bottom surface of the silicon carbide semiconductor substrate, the bottom surface opposite the top surface;
• and
• a planar gate structure including a gate dielectric and a gate runner adjacent a p-type channel region, wherein the gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure, and wherein the gate runner is electrically insulated from the channel region, the source structure and the source contact structure by the gate dielectric, the gate running overlapping the channel region and at least part of the source contact structure.