Back to results
US 2022/0278196 A1Published application
Semiconductor devices and methods of fabrication thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Jiun Kuang, Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei WU
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.
Claims26
A semiconductor device, comprising:
- a nanosheet stack comprising:
- two or more channel layers;
- and
- a hard mask layer disposed over the two or more channel layers, wherein the hard mask layer has a first surface facing the two or more channel layers, and
- a second surface opposing the first surface;
- a gate dielectric layer formed around the two or more channel layers and on the first surface of the hard mask layer;
- a sidewall spacer in contact with the second surface of the hard mask layer;
- an inner spacer disposed between the first surface of the hard mask layer and the two or more channel layers;
- and
- a boundary feature in contact with the inner spacer, the two or more channel layers, and the hard mask layer, wherein the hard mask layer has a third surface connecting the first and second surfaces, and the boundary feature is in contact with the third surface of the hard mask layer.
7 more elements
(canceled)
(canceled)
A semiconductor device, comprising:
- a first source/drain feature;
- two or more first channel layers in contact with the first source/drain feature, wherein each of the two or more first channel layers includes:
- a first surface;
- a second surface opposing the first surface;
- and
- an end surface connecting the first surface and second surface, wherein the first surface and second surfaces are exposed to air gaps at portions adjacent the end surface;
- a hard mask layer formed over the two or more first channel layers;
- a gate dielectric layer formed on the two or more first channel layers and the hard mask layer, wherein one of the air gaps is formed between the hard mask layer and a topmost of the two or more first channels near the end surface;
- a gate electrode layer formed on the gate dielectric layer;
- a fin sidewall spacer in contact with the hard mask layer and the two or more first channel layers, wherein the fin sidewall spacer is exposed to the air gaps;
- and
- a boundary structure in contact with the hard mask layer and the two or more first channel layers, wherein the air gaps are formed between the boundary structure and the fin sidewall spacer, and between the gate dielectric layer and the first source/drain feature.
9 more elements
(canceled)
(canceled)
(canceled)
A method for forming a semiconductor device, comprising:
- forming fin structures including two or more channel layers and a hard mask layer over the two or more channel layers with spacing layers formed between adjacent channel layers and the hard mask layer;
- forming a sacrificial gate structure over the fin structures and sidewall spacers on the sacrificial gate structure;
- recess etching the fin structures;
- removing a portion of the spacing layers to form inner spacers between the of channel layers and the hard mask layer;
- forming source/drain features;
- removing the sacrificial gate structure;
- forming a replacement gate structure comprising:
- depositing a gate dielectric layer on the two or more channel layers and the hard mask layer;
- and
- depositing a gate electrode layer over the gate dielectric layer;
- forming a trench along a direction perpendicular to the replacement gate structure to remove a portion of the fin structures;
- and
- etching the inner spacers to form air gaps.
10 more elements
(canceled)
Dependencies are inferred from the claim text.