Ferroelectric memory and memory array device with multiple independently controlled gates

Abstract

A multi-gate ferroelectric memory comprises a fin-shaped channel layer, a front ferroelectric layer disposed on one side of the fin-shaped channel layer, a back ferroelectric layer disposed on another side of the fin-shaped channel layer, a front gate attached to the front ferroelectric layer and away from the fin-shaped channel layer, wherein the front gate is configured to connect a word line, and a back gate attached to the back ferroelectric layer and away from the fin-shaped channel layer, wherein the back gate is configured to connect a bit line. The present disclosure further discloses a memory array device, comprises a plurality of the multi-gate ferroelectric memories arranged as an array, a plurality of word lines and a plurality of bit lines.

Dependencies are inferred from the claim text.