Semiconductor package including a dummy chip

A semiconductor package comprising:

• a base structure;
• a lower semiconductor chip on the base structure;
• an upper semiconductor chip on the lower semiconductor chip;
• a connecting structure comprising a lower pad on the lower semiconductor chip, an upper pad under the upper semiconductor chip, and a connecting bump between the lower pad and the upper pad;
• a lower adhesive layer comprising a lower adhesive portion between the lower semiconductor chip and the upper semiconductor chip, and a lower protrusion portion at opposite sides of the lower adhesive portion, to surround at least one of upper portions of opposite side surfaces of the lower semiconductor chip and lower portions of opposite side surfaces of the upper semiconductor chip;
• a dummy chip on the upper semiconductor chip;
• a solder between the upper semiconductor chip and the dummy chip;
• and
• a molding layer surrounding a side surface of the dummy chip and the solder.

A semiconductor package comprising:

• a base structure;
• a connecting terminal comprising a base pad at a bottom portion of the base structure, and a base bump under the base pad;
• a lower semiconductor chip on the base structure, the lower semiconductor chip comprising a semiconductor substrate, a first wiring layer under the semiconductor substrate, a first lower protective layer under the first wiring layer, a first upper protective layer on the semiconductor substrate, and a through via extending through the semiconductor substrate and the first upper protective layer;
• an upper semiconductor chip on the lower semiconductor chip, the upper semiconductor chip comprising a semiconductor substrate, a second wiring layer under the semiconductor substrate, a second lower protective layer under the second wiring layer, and a first upper protective layer on the semiconductor substrate;
• a connecting structure comprising a lower pad on the lower semiconductor chip and connected to the through via of the lower semiconductor chip, an upper pad under the upper semiconductor chip and connected to the second wiring layer of the upper semiconductor chip, and a connecting bump between the lower pad and the upper pad to interconnect the lower pad and the upper pad;
• a lower adhesive layer comprising a lower adhesive portion between the lower semiconductor chip and the upper semiconductor chip, and a lower protrusion portion at opposite sides of the lower adhesive portion to surround at least one of upper portions of opposite side surfaces of the lower semiconductor chip and lower portions of opposite side surfaces of the upper semiconductor chip;
• a dummy chip on the upper semiconductor chip;
• an upper adhesive layer comprising an upper adhesive portion between the upper semiconductor chip and the dummy chip, and an upper protrusion portion at opposite sides of the upper adhesive portion to surround lower portions of opposite side surfaces of the dummy chip;
• and
• a molding layer at opposite sides of the dummy chip to surround upper portions of the opposite side surfaces of the dummy chip and the upper protrusion portion,
• wherein a height of the upper adhesive portion is smaller than a height of the lower adhesive portion, and
• wherein a width of the upper protrusion portion is smaller than a width of the lower protrusion portion.