Integrated Circuit Layouts with Fill Feature Shapes

A method comprising:

• initializing a layout for fabricating an integrated circuit;
• inserting a plurality of fill cells that represent conductive features in one or more inter-level dielectric (ILD) layers into the layout, wherein the plurality of fill cells includes a plurality of fill line shapes that correspond to metal lines of the integrated circuit;
• thereafter inserting a design that includes a plurality of functional shapes into the layout;
• removing a conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality of functional shapes;
• after the removing of the conflicting subset of the plurality of fill line shapes of the plurality of fill cells, adding new fill line shapes that represent conductive features in the one or more ILD layers to the layout, wherein the new fill line shapes are spaced apart from the functional shapes in a top view of the layout;
• and
• providing the layout that includes the plurality of fill cells, the new fill line shapes, and the design for fabricating the integrated circuit.

A non-transitory machine-readable medium storing instructions that, when executed by a processing resource, cause the processing resource to:

• initialize a layout for fabricating an integrated circuit;
• determine a feature density of the layout;
• in response to determining the feature density, insert fill cells into the layout, wherein the fill cells include a first plurality of fill line shapes that define conductive lines in a first layer of the integrated circuit;
• thereafter insert a functional design into the layout;
• remove a subset of the first plurality of fill line shapes that conflict with the functional design;
• insert a second plurality of fill line shapes into the layout that define conductive lines in the first layer of the integrated circuit;
• and
• provide the layout that includes the fill cells, the functional design, and the second plurality of fill line shapes for fabricating of the integrated circuit, wherein the feature density of the layout is not less than a minimum feature density.