Embedded test apparatus for high speed interfaces

A method for testing an integrated circuit, whereby the method comprises:

• receiving an input signal at a receive unit to be tested, and storing the input signal at a predetermined point in time;
• providing a filtered input signal based on the input signal;
• applying an error correction to the input signal, thereby generating an error corrected signal;
• comparing the error corrected signal with an expectation value;
• outputting an error message when the filtered input signal does not correspond to the expectation value;
• supplying the receive unit to be tested with an adjustable voltage or an adjustable current;
• and
• varying the predetermined point in time and the adjustable voltage or the adjustable current.

An integrated circuit, comprising:

• a receive unit including an input terminal, an output terminal, and a control terminal, the input terminal configured to receive an input signal;
• a filter including an filter input and a filter output, the filter input coupled to the output terminal of the receive unit, and the filter output configured to provide a filtered input signal that is based on the input signal;
• a processor having a processor input coupled to filter output and configured to provide an adjustment value and a failure message that are based on the filtered input signal and an expectation value;
• a communication path coupling an output of the processor back to the control terminal of the receive unit;
• a power supply configured to provide an adjustable voltage or an adjustable current to a location on the communication path;
• and
• an adjustment unit disposed at the location on the communication path and coupled to the power supply, the adjustment unit configured to vary the adjustable voltage or the adjustable current, respectively, based on the adjustment value.