Voltage hold circuit, voltage monitoring circuit, and semiconductor integrated circuit

A voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit comprising:

• a generation circuit configured to generate a reset voltage signal which varies according to the input voltage signal;
• a hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle;
• and
• a reset circuit configured to reset an output voltage based on the reset voltage signal in the reset period every the processing cycle.

A voltage hold circuit configured to hold a voltage value for an input voltage signal, the voltage hold circuit comprising:

• a determination circuit configured to determine an increase or a decrease in the input voltage signal;
• a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal every first period, the determination circuit determining an increase in the input voltage signal in the first period;
• and
• a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal every second period, the determination circuit determining a decrease in the input voltage signal in the second period.