One direction-shift register aliasing table circuit suitable for use in microprocessors
AssigneeTobb Ekonomi Ve Teknoloji Universitesi
InventorsOguz ERGIN, Ilker POLAT
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Abstract
Disclosed are hardware configurations of the Register Aliasing Table (RAT) which are suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents Write After Read (WAR), Write After Write (WAW), Read After Write(RAW) dependencies. The Register Aliasing Table provides a circuit which consumes less energy, uses less space and has low latency compared to the applications in the state of the art.
Claims3
Register aliasing table which is suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents write after read, write after write, read after write risks, wherein the register aliasing table comprises:
- a pre-determined number of adjacently ordered printer drivers which are adapted to be activated during writing process,
- a pre-charge block ordered side by side with same number of buses connected to the printer drivers which are adapted to ensure the buses to wait in a stable manner when reading or writing is not performed,
- a SRAM cell block which comprises cell groups that are interconnectedly arranged with each other such that they have the same number of columns connected to the pre-charge blocks with the same number of buses and have another number of rows determined previously,
- a second decoder which determines the row in which the information in the cell group will be copied and is adapted for executing the commands that informs about which row will be referred for information to perform the process, has an outlet that is connected to each row of SRAM cell block,
- sense amplifiers which are connected to SRAM cell block in proportion with the number of columns via buses, are arranged adjacent to each other in proportion with the number of adapted columns for bringing the low output to a level that can be read,
- multiplexers which are connected to the sense amplifiers in proportion with the number of columns via buses, are arranged adjacent to each other in proportion with the number of adapted columns for selecting from which 7-bit SRAM cell group will the output required for reading be taken,
- a first decoder which determines in which cell group in the SRAM cell block, the reading and writing operations will be performed and determines which of said peripheral units arranged adjacent to each other will operate during operations.
Dependencies are inferred from the claim text.